A vector network analyzer (VNA) is conventionally used to measure scattering parameters by presenting a stimulus to a device under test (DUT) and measuring the DUT's response to the stimulus. The resulting scattering parameters mathematically define electrical behavior in terms of reflection and transmission coefficients of the measured DUT over a frequency range of interest. It is typically not possible to directly connect the DUT to the VNA to obtain a measurement of only the DUT. It is more typical that there are intermediate connectors, cables, transmission lines and other circuitry between the stimulus and measurement ports of the VNA and the DUT. For purposes of the present disclosure, the general term that is used for all of the intermediate connections between the VNA and the measured device is “an adapter”. At low frequencies the electrical behavior of the adapter may not significantly affect the measurement of the DUT. At high frequencies, however, the response of the adapter as cascaded with the DUT for which a measurement is desired, can be as significant or more significant that the response attributable to the DUT itself. It is therefore imperative that the measurement process be able to account for and eliminate the effects of the adapter to obtain a measurement of the electrical behavior of the DUT in isolation. This process is called de-embedding the DUT from the adapter or characterizing the DUT.
Once the DUT is characterized, a circuit designer is able to use the mathematical representation of the electrical behavior of the DUT together with a modeled or measured circuit to predict the electrical behavior of the DUT in combination with the modeled or measured circuit. This practice is termed “embedding” and is especially valuable because circuit combinations may be designed and tested without expending the time, money, and effort to build and test a prototype. Obviating the practice of building prototypes that do not operate as desired reduces time to market because it increases the probability that a circuit that is eventually built will optimally perform for its intended purpose.
Agilent Technologies, Inc. application note 1364-1 entitled “De-embedding and Embedding S-Parameter Networks Using a Vector Network Analyzer” presents a process for de-embedding a measurement of a DUT from the interfering electrical effects of intermediate adapters and is hereby incorporated by reference. With specific reference to FIG. 1 of the drawings, there is shown a test set-up for a 2N-port DUT 100. A first adapter 102, also having 2N adapter ports is cascaded with the 2N-port DUT 100 as well as a 2N port second adapter 110. The cascaded combination of the first adapter 102, the DUT 100, and the second adapter 110 is connected to VNA 106. The VNA 106 has 2N test ports 1161 through 1162N and comprises a stimulus 112, a test set 104, a reference channel receiver 94, and a plurality of test channel receivers 961 through 962n. The output of the stimulus 112 is connected to first signal separating device 92. The forward orientation of the first signal separating device 92 samples a small amount of output power from the stimulus 112 and feeds the sampled signal to the reference channel receiver 94 to provide a reference measurement. Most of the output power from the stimulus 112, however, is delivered to a pole of a single pole, multiple throw switch 98. The switch 98 selectively connects the stimulus signal to one of a plurality of switch output ports 1141 through 1142n. FIG. 1 shows an embodiment of the switch 98 having as many output ports 114 as there are adapter ports to measure in the cascaded combination of the first adapter 102, the DUT 100, and the second adapter 110. The test set 104 also comprises a plurality of single pole double throw switches 901 through 902n connected to each switch output port 114. The single pole double throw switches 901 through 902n permit a signal delivered by the stimulus 112 to be fed to any port of the cascaded combination while the remaining ports are terminated in one of a plurality of respective characteristic impedances 1201 through 1202n. Accordingly, a signal from the stimulus 112 may be fed to any test port 116 through an appropriate configuration of switch 98 and switches 901 through 902n. Concurrently, all remaining test ports 116 may be terminated to its characteristic impedance 120. FIG. 1 shows the signal from the stimulus 112 being fed to port 1 of the first adapter 102 while all remaining first and second adapter ports that are connected to test ports 116 are terminated with a characteristic impedance. Each test port 116 comprises a respective test channel signal-separating device 881 through 882n. A main arm of each test channel signal-separating device 88 is connected to a respective test port 116. As illustrated in FIG. 1, the first adapter ports 1 through n and the second adapter ports n+1 through 2n are each connected to one of the test ports 116. The sampling arm of each test channel signal-separating device 88 is connected to each one of a respective plurality of VNA test channel receivers 961 through 962n. The test channel receivers 96 measure the output power present at each test port 116. A reverse orientation of the signal separating devices 88 permits measurement of both reflected and transmitted signals from the adapter ports to which the VNA test channel is connected. As a signal from the stimulus 112 is swept across a desired frequency bandwidth, the ratio of power measured at the test channel receivers 96 relative to the power measured at the reference channel receiver 94 is obtained. As shown in the illustration of FIG. 1, it is desirable to have as many VNA test ports 116 as there are adapter ports to measure. As the number of ports increases, however, this luxury becomes economically prohibitive. Accordingly, it is conventional practice to share VNA test ports 116 at the expense of speed to make the same measurements.
FIG. 1 illustrates the DUT 100 having input device ports 1081 through 108n and device ports 108n+1 and 108n+1 through 1082n connected to ports n+1 through 2n of the first adapter 102 and ports 1 through n of the second adapter 110, respectively. The first and second adapters 102, 110 are cascaded with the DUT 100 on either side so that all device ports 108 are connected to the VNA test ports 116 through either the first or second adapters 102, 110. As one of ordinary skill in the art appreciates, the first and second adapters 102, 110 represent all of the connectors, cabling and circuitry required connecting the DUT 100 to the VNA 106. If the S-parameters for the first adapter 102 and the second adapter 110 are known either through measurement or modeling, one can measure the cascaded combination of the first and second adapters 102, 110 with the DUT 100. The S-parameters may then be converted to the corresponding scattering transfer parameters also termed transmission parameters or T-parameters. The matrix TX represents the T-parameters of the first adapter 102, the matrix TY represents the T-parameters of the second adapter 110, and Tc represents the T-parameters of the cascaded combination of first and second adapters 102, 110 and the DUT 100. The T-parameters of the DUT, represented by the matrix TD, may be mathematically extracted from these measurements by using:[Tc]=[TX]·[TD]·[TY].
Solving for TD:[TD]=[TX]−1·[Tc]·[TY]−1
The T-parameter matrix for the DUT, TD, may then be converted into its corresponding S-parameter matrix, SD.
It is known to use the same principles to de-embed and embed a DUT having more than four ports. U.S. Pat. No. 5,578,932 entitled “Method and Apparatus for Providing and Calibrating a Multi-port Network Analyzer” discloses a method and apparatus to perform measurements of an N-port DUT using a 2-port VNA. One of the limitations of the prior art embedding and de-embedding processes is that the DUT must be have an even number of ports Additionally, the first and second adapters that connect the DUT with the VNA must also have the same even port configuration as the DUT. The physical world, however, does not always cooperate with these restrictions. There are many devices that are used in electrical circuits that have an odd number of device ports. Specific examples of DUTs that present a measurement challenge as a result of an odd number of device ports are baluns, terminated directional couplers, power dividers, switches, digital devices and some filters. The prior art does not disclose how to properly represent these devices in matrices that may be manipulated as part of the conventional de-embedding and embedding process. Using the conventional approach, the matrix that represents the electrical behavior of the first adapter is a different size than the matrix that represents the electrical behavior of the second adapter. Accordingly, the process presented in the prior art cannot be performed on the matrices that result from the measurements made of the first and second adapters. Under the prior art, embedding and de-embedding of devices having an odd number of input or output device ports is simply not possible. There is a need, therefore, for a general process to permit embedding and de-embedding of devices with an odd number of input or output ports.
The characterization process as is conventionally known and briefly described above performs quite well for the case where all of the adapters, such as the adapter X and the adapter Y, are electrically isolated from each other. A specific example of measurements that present a challenge to the methods, apparatus', and models disclosed in the prior art are DUTs that are disposed on a semi-conductor wafer. In order to access on-wafer DUTs, it is necessary to make measurements through one or more adapter circuits comprising connectors and cabling to a wafer probing station, transmission lines to the probes, and through the probes themselves to all ports of the DUT. It is likely that there is leakage and electrical interaction between the adapter circuits to all ports of the DUT. As an example, adjacent probes may radiate and energy present on one probe may couple to an adjacent probe. The prior art representation of the first and second adapters 102, 110 relative to the DUT 100 assumes that the first adapter 102 is electrically isolated from the second adapter 110. This isolation assumption accurately reflects the conventional situation where one or more input connectors connect one port of the VNA to input ports of the DUT and one or more output connectors connect another port of the VNA to output ports of the DUT. This isolation assumption, however, does not properly apply to the physical reality of on-wafer measurements where there may be interaction or coupling between the adapters that connect the input and output ports of the DUT 100 to the VNA 106. The limitations of the prior model as applied to the reality of the on-wafer measurement create errors in the resulting DUT characterization. Use of an erroneous characterization to predict electrical behavior of the DUT 100 in combination with another circuit produces results that are less reliable than what would be produced using an accurate characterization. Reliable and accurate characterization reduces the disparity between predicted behavior and actual behavior saving time and money during the design process. There is a need, therefore, for a method, apparatus, and article of manufacture to characterize a DUT 100 that is embedded in surrounding circuitry more accurately than in the prior art.
Also in the prior art, a VNA measurement port is assigned to a specific port number on the DUT and is thereafter fixed by convention. The user must adapt the cabling and hook-ups to the appropriate DUT ports in order to obtain valid measurements for different port numbering. For simple DUTs, this is merely an inconvenience and requires that the user give thought to the most efficient connections to the DUT with the possible addition of cabling and matching connectors to effect the connections of the device ports to the proper VNA measurement ports. The additional cabling required presents the possibility of non-repeatable errors that are not fully compensated by the measurement process. It is desirable, therefore, to have a more flexible port assignment process when making VNA measurements. In the case of DUTs with higher numbers of device ports, the inconvenience presented increases geometrically with each increase in the number of device ports. In the case of DUTs that are on-wafer, this inconvenience becomes unworkable because the port assignment and probe access pad orientation from one DUT to an adjacent DUT may not be the same. The intermediate adapter comprising the cabling and probes, however, remains fixed. A possible solution to the challenge is to manually disconnect the cabling and reconnect to the proper VNA ports or place a complex switch in the adapter circuitry. Besides being either prohibitively cumbersome, time consuming or expensive, the change to the connections and bends in the cables introduces either measurement errors for which the compensation mechanism requires additional measurement and error correction or non-repeatable errors than cannot be ascertained and eliminated. There is a need, therefore, for a method, system, and apparatus that permits flexible assignment of measurement ports of the VNA to the device ports of the adapters and DUT.
The present invention endeavors to address these and other limitations and shortcomings of the prior art.